TinyTPU
LiveOverview
TinyTPU is a browser-based hardware visualization project that runs a real synthesizable SystemVerilog systolic array in the browser. The RTL is compiled to WebAssembly and visualized cycle-by-cycle so users can watch matrix multiplication move through processing elements.
The project connects low-level computer architecture, hardware simulation, WebAssembly, and modern frontend visualization into one interactive demo.
Architecture
Challenges & Solutions
Hardware architecture is difficult to explain through static diagrams - people struggle to see data flow through a systolic array.
Compiled the actual RTL to WebAssembly and animated processing element activations, partial sums, and data movement cycle-by-cycle.
Frontend demos often fake the backend logic with synthetic animations.
The browser executes the actual Verilog RTL compiled to WASM - no simulation layer, the hardware behavior is real.
Features
- Real synthesizable SystemVerilog 4×4 systolic array
- RTL compiled to WebAssembly via Verilator + Emscripten
- Cycle-by-cycle processing element animation in the browser
- Matrix input and partial sum visualization
- Astro + React frontend - no backend required
- Verified with cocotb and NumPy
- Live Vercel deployment
